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 Single-chip Type with built-in FET Switching Regulator Series
Flexible Step-down Switching Regulators with Built-in Power MOSFET
BD9778F, BD9778HFP, BD9001F, BD9781HFP
No.10027EBT41
Overview The flexible step-down switching regulator controller is a switching regulator controller designed with a high-withstand-voltage built-in POWER MOS FET, providing a free setting function of operating frequency with external resistor. This switching regulator controller features a wide input voltage range (7 V to 35 V or 7 V to 48 V) and operating temperature range (-40C to +125C or -40C to +95C). Furthermore, an external synchronization input pin (BD9781HFP) enables synchronous operation with external clock.
Features 1) 2) 3) 4) 5) 6) 8) 9) 10) 11) 12) 13) 14) 15) Minimal external components Wide input voltage range: 7 V to 35 V (BD9778F/HFP and BD9781HFP), 7 V to 48 V (BD9001F) Built-in P-ch POWER MOS FET Output voltage setting enabled with external resistor: 1 to VIN Reference voltage accuracy: 2% Wide operating temperature range: -40C to +125C (BD9778F/HFP and BD9781HFP), -40C to +95C (BD9001F) Low dropout: 100% ON Duty cycle Standby mode supply current: 0 A (Typ.) (BD9778F/HFP and BD9781HFP), 4 A (Typ.) (BD9001F) Oscillation frequency variable with external resistor: 50 to 300 kHz (BD9001F), 50 to 500 kHz (BD9778F/HFP and BD9781HFP) External synchronization enabled (only on the BD9781HFP) Soft start function : soft start time fixed to 5 ms (Typ.)) Built-in overcurrent protection circuit Built-in thermal shutdown protection circuit High power HRP7 package mounted (BD9778HFP and BD9781HFP) Compact SOP8 package mounted (BD9778F and BD9001F)
Applications All fields of industrial equipment, such as Flat TV , printer, DVD, car audio, car navigation, and communication such as ETC, AV, and OA.
Product lineup Item Output current Input range Oscillation frequency range External synchronization Standby function Operating temperature Package BD9778F/HFP 2A 7V ~ 35V 50 ~ 500kHz Not provided Provided -40C ~ +125C SOP8 / HRP7 BD9001F 2A 7V ~ 48V 50 ~ 300kHz Not provided Provided -40C ~ +95C SOP8 BD9781HFP 4A 7V ~ 35V 50 ~ 500kHz Provided Provided -40C ~ +125C HRP7
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1/16
2010.02 - Rev. B
BD9778F, BD9778HFP, BD9001F, BD9781HFP
Absolute Maximum Ratings(Ta = 25C) Parameter BD9778F/HFP,BD9781HFP Power supply BD9001F voltage Output switch pin voltage Output switch current
BD9778F/HFP, BD9001F BD9781HFP
Technical Note
Symbol VIN VSW ISW VEN/SYNC,VEN VRT,VFB,VINV Pd Topr Tstg Tjmax
EN/SYNC, EN pin voltage RT, FB, INV pin voltage Power dissipation
HRP7 SOP8
Operating temperature BD9778F/HFP,BD9781HFP range BD9001F Storage temperature range Maximum junction temperature
Limits 36 50 VIN 2 4 VIN 7 5.5 0.69 -40 ~ +125 -40 ~ +95 -55 ~ +150 150
Unit V V
*1 *1
A V
*2 *3
W C C C
*1 Should not exceed Pd-value. *2 Reduce by 44mW/C over 25C, when mounted on 2-layer PCB of 70 X 70 X 1.6 mm3. (PCB incorporates thermal via. Copper foil area on the front side of PCB: 10.5 X 10.5 mm2. Copper foil area on the reverse side of PCB: 70 X 70 mm2) *3 Reduce by 5.52 mW/C over 25C, when mounted on 2-layer PCB of 70 X 70 X 1.6 mm3.
Recommended operating range Parameter Operating power supply voltage Output switch current Output voltage (ON Duty) Oscillation frequency Oscillation frequency set resistance BD9778F/HFP 7 ~ 35 ~2 6 ~ 100 50 ~ 500 40 ~ 800 BD9001F 7 ~ 48 ~2 6 ~ 100 50 ~ 300 100 ~ 800 BD9781HFP 7 ~ 35 ~4 6 ~ 100 50 ~ 500 39 ~ 800 Unit V A % kHz k
Possible operating range Parameter Operating power supply voltage BD9778F/HFP 5 ~ 35 BD9001F 7 ~ 48 BD9781HFP 5 ~ 35 Unit V
Electrical characteristics BD9778F/HFP (Unless otherwise specified, Ta = -40C to +125C, VIN =13.2 V, VEN = 5 V) Parameter Symbol Min. 2 0.98 0.96 -1 2.4 -5.0 70 82 0.8 Limits Typ. Max. 0 10 3 4.2 0.53 4 0 1.00 1.00 0.5 2.5 0.05 -3.0 120 5 102 1 1.7 13 0.9 30 1.02 1.04 0.10 -0.5 170 122 2.6 50 Unit A mA A A V V % A V V mA A mS kHz % V A Condition VEN=0V,Ta=25C IO=0A ISW=50mA * Design assurance VIN=35V,VEN=0V VFB=VINV,Ta=25C VFB=VINV VIN=5 ~ 35V VINV=1.1V VINV=0.5V VINV=1.5V VFB=1.5V,VINV=1.5V VFB=1.5V,VINV=0.5V * Design assurance RT=390k VIN=5 ~ 35V VEN=5V
ISTB Standby circuit current IQ Circuit current [SW block] RON POWER MOS FET ON resistance IOLIMIT Operating output current of overcurrent protection IOLEAK Output leak current [Error Amp block] VREF1 Reference voltage 1 VREF2 Reference voltage 2 VREF Reference voltage input regulation IB Input bias current VFBH Maximum FB voltage VFBL Minimum FB voltage IFBSINK FB sink current IFBSOURCE FB source current TSS Soft start time [Oscillator block] FOSC Oscillation frequency FOSC Frequency input regulation [Enable block] VEN Threshold voltage IEN Sink current
* Not designed to be radiation-resistant.
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2/16
2010.02 - Rev. B
BD9778F, BD9778HFP, BD9001F, BD9781HFP
BD9001F (Unless otherwise specified, Ta=-40C ~ +95C,VIN=13.2V, VEN=5V) Parameter Symbol Min. 2.5 0.98 0.96 -1 2.4 -5.0 70 82 0.8 Limits Typ. Max. 4 10 3 4.2 0.6 4 1.00 1.00 0.5 2.5 0.05 -3.0 120 5 102 2 1.7 13 1.2 1.02 1.04 0.10 -0.5 170 122 2.6 50 Unit A mA A V V % A V V mA A ms kHz % V A Condition VEN=0V,Ta=25C IO=0A ISW=50mA * Design assurance VFB=VINV,Ta=25C VFB=VINV VIN=7 ~ 48V VINV=1.1V VINV=0.5V VINV=1.5V VFB=1.5V,VINV=1.5V VFB=1.5V,VINV=0.5V * Design assurance RT=390k VIN=7 ~ 48V
Technical Note
Standby circuit current ISTB IQ Circuit current [SW block] RON POWER MOS FET ON resistance IOLIMIT Operating output current of overcurrent protection [Error Amp block] VREF1 Reference voltage 1 VREF2 Reference voltage 2 VREF Reference voltage input regulation IB Input bias current VFBH Maximum FB voltage VFBL Minimum FB voltage IFBSINK FB sink current IFBSOURCE FB source current Soft start time Tss [Oscillator block] FOSC Oscillation frequency FOSC Frequency input regulation [Enable block] VEN Threshold voltage IEN Sink current
* Not designed to be radiation-resistant.
VEN =5V
BD9781HFP (Unless otherwise specified, Ta=-40C ~ +125C,VIN=13.2V,VEN/SYNC=5V) Parameter Symbol Min. 4 0.98 0.97 -1 2.4 -5.0 70 82 0.8 Limits Typ. Max. 0 10 8 3 0.5 8 0 1.00 1.00 0.5 2.5 0.05 -3.0 120 5 102 1 1.7 35 150 0.9 30 1.02 1.03 0.10 -0.5 170 122 2.6 90 Unit A mA A A V V % A V V mA A mS kHz % V A kHz Condition VEN/SYNC=0V,Ta=25C IO=0A ISW=50mA * Design assurance VIN=35V,VEN/SYNC=0V VFB=VINV,Ta=25C VFB=VINV VIN=5 ~ 35V VINV=1.1V VINV=0.5V VINV=1.5V VFB=1.5V,VINV=1.5V VFB=1.5V,VINV=0.5V * Design assurance RT=390k VIN=5 ~ 35V VEN/SYNC=5V FEN/SYNC=150kHz
ISTB Standby circuit current IQ Circuit current [SW block] RON POWER MOS FET ON resistance IOLIMIT Operating output current of overcurrent protection IOLEAK Output leak current [Error Amp block] Reference voltage1 VREF1 VREF2 Reference voltage2 VREF Reference voltage input regulation IB Input bias current VFBH Maximum FB voltage VFBL Minimum FB voltage IFBSINK FB sink current IFBSOURCE FB source current TSS Soft start time [Oscillator block] FOSC Oscillation frequency FOSC Frequency input regulation [Enable/Synchronizing input block] VEN/SYNC Threshold voltage IEN/SYNC Sink current FSYNC External synchronizing frequency
* Not designed to be radiation-resistant.
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3/16
2010.02 - Rev. B
BD9778F, BD9778HFP, BD9001F, BD9781HFP
Reference data
Technical Note
OSCILLATING FREQUENCY : fosc[kHz]
1.020 REFERENCE VOLTAGE : VREF[V] 1.015 1.010 1.005 1.000 0.995 0.990 0.985 0.980 -50 -25 0 25 50 75 100 125
600 500 400 300 200 100 0 -50
390k 910k 91k
10 STAND-BY CURRENT : ISTB[A]
39k
9 8 7 6 5 4 3 2 1 0 0 5 10 15 20
25 -40 VCC=12V Istb=0.14A 125
-25
0
25
50
75
100 125
25
30
35
40
AMBIENT TEMPERATURE : Ta[ ]
AMBIENT TEMPERATURE : Ta[ ]
INPUT VOLTAGE : VIN[V]
Fig.1 Output reference voltage vs. Ambient temprature(All series)
Fig.2 Frequency vs. Ambient temperature(All series)
Fig.3 Standby current(BD9781HFP)
10 STAND-BY CURRENT : ISTB[A]
STAND-BY CURRENT : ISTB[A]
40
125
4 CIRCUIT CURRENT : ICC[mA]
9 8 7 6
125
30
25
3
-40 25 125
5 4 3 2 1 0 0 5
25 -40 VCC=12V Istb=0.14A
20
-40
2
10
1
0
10 15 20 25 30 INPUT VOLTAGE : VIN[V]
35
40
0
10
20
30
40
50
60
0
5
10
15
20
25
30
35
40
INPUT VOLTAGE : VIN[V]
INPUT VOLTAGE : VIN[V]
Fig.4 Standby current(BD9778F/HFP)
Fig.5 Standby current(BD9001F)
Fig.6 Circuit current(BD9781HFP)
4
CIRCUIT CURRENT : ICC[mA] CIRCUIT CURRENT : ICC[mA]
-40 25 125
4
1.8 1.6
FET ON RESISTANCE : RON[]
3
3
125 -40 25
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 OUTPUT CURRENT : IO[A]
Ta=-40 Ta=125 Ta=25
2
2
1
1
0
0
5
10 15 20 25 30 INPUT VOLTAGE : VIN[V]
35
40
0
10
20 30 40 50 INPUT VOLTAGE : VIN[V]
60
Fig.7 Circuit current(BD9778F/HFP)
Fig.8 Circuit current(BD9001F)
Fig.9 ON resistance VIN=5V(BD9781HFP)
1.8
1.8
FET ON RESISTANCE : RON[] FET ON RESISTANCE : RON[]
1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0
0.5 1.0 1.5 2.0 2.5
Ta=-40 Ta=125 Ta=25
FET ON RESISTANCE : RON[]
1.6 1.4 1.2 1.0 0.8 0.6 0.4
Ta=-40 Ta=25 Ta=125
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2
Ta=-40 Ta=25 Ta=125
0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 OUTPUT CURRENT : IO[A]
0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
OUTPUT CURRENT : IO[A]
OUTPUT CURRENT : IO[A]
Fig.10 ON resistance VIN=7V (BD9781HFP)
Fig.11 ON resistanceVIN=13.2V (BD9781HFP)
Fig.12 ON resistance VIN=5V (BD9778F/HFP)
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4/16
2010.02 - Rev. B
BD9778F, BD9778HFP, BD9001F, BD9781HFP
1.8
FET ON RESISTANCE : RON[]
FET ON RESISTANCE : RON[]
Technical Note
1.8
FET ON RESISTANCE : RON[]
1.8 1.6 1.4 1.2 1.0 0.8
Ta=125
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0
0.5 1.0 1.5 2.0 OUTPUT CURRENT : IO[A] 2.5
Ta=125 Ta=25 Ta=-40
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0
0 0.5 1 1.5 2 OUTPUT CURRENT : IO[A] 2.5
Ta=125 Ta=25
0.6
Ta=25
0.4 0.2 0.0 0.0
Ta=-40
Ta=-40
0.5 1.0 1.5 2.0 OUTPUT CURRENT : IO[A]
2.5
Fig.13 ON resistance VIN=7V (BD9778F/HFP)
Fig.14 ON resistance VIN=13.2V (BD9778F/HFP)
Fig.15 ON resistance VIN=7V (BD9001F)
1.8
CONVERSION EFFICIENCY [%]
100
CONVERSION EFFICIENCY [%]
100
5V output
FET ON RESISTANCE : RON[]
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0
0 0.5 1 1.5 2 OUTPUT CURRENT : IO[A] 2.5
Ta=-40 Ta=125 Ta=25
5V output 3.3V output
90 80 70 60 50 40 30 20 10 0 0.0
0.5
3.3V output
90 80 70 60 50 40 30 20 10
2.5V output 1.5V output
2.5V output
1.0 1.5 2.0 2.5 OUTPUT CURRENT : IO[A]
3.0
0
0
1.5 0.5 1.0 OUTPUT CURRENT : IO[A]
2.0
Fig.16 ON resistance VIN=13.2V
(BD9001F)
Fig.17 IO vs Efficiency(VIN=12V,f=200kHz)
(BD9781HFP)
Fig.18 IO vs Efficiency(VIN=12V,f=100kHz)
(BD9778F/HFP)
100
CONVERSION EFFICIENCY [%]
6
5V output Ta=25 Ta=-40
6
Ta=25
90 80 70 60 50 40 30 20 10 0
0
OUTPUT VOLTAGE : VO[V]
5 4
Ta=125
5
Ta=-40
3.3V output 2.5V output
OUTPUT VOLTAGE : VO[V]
4 3 2 1 0
Ta=125
3 2 1 0
0.4 0.8 1.2 1.6 OUTPUT CURRENT : IO[A]
2
0
1
2 3 4 5 6 OUTPUT CURRENT : IO[A]
7
0
1 2 3 4 OUTPUT CURRENT : IO[A]
5
Fig.19 IO vs Efficiency(VIN=12V,f=100kHz) Fig.20 Current capacitance(VIN=12V,Vo=5V,f=100kHz) Fig.21 Current capacitance(VIN=12V,Vo=5V,f=100kHz)
(BD9001F) (BD9781HFP) (BD9778F/HFP)
6 5 4
Ta=125 Ta=25 Ta=-40
OUTPUT VOLTAGE : VO[V]
3 2 1 0
0
1 2 3 4 OUTPUT CURRENT : IO[A]
5
Fig.22 Current capacitance(VIN=12V,Vo=5V,f=100kHz)
(BD9001F)
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5/16
2010.02 - Rev. B
BD9778F, BD9778HFP, BD9001F, BD9781HFP
Block diagram / Application circuit / Pin assignment (BD9778F) (BD9778HFP)
Technical Note
PVIN
8
VIN EN ON/OFF L:OFF H:ON
1
5
VIN
EN ON/OFF L:OFF H:ON
1
7
220F
1F Vref
220F
1F Vref
SOFT START 23k 4 10k 150k GND EN PVIN RT 4700pF
SOFT START 23k
INV
ERROR AMP
INV
ERROR AMP
+ +
Vref
+
PWM COMPARATOR LATCH RESET DRIVER SW
5 33H
VO
2
TSD
10k 150k 4700pF
+ +
Vref
+
PWM COMPARATOR LATCH RESET DRIVER SW
33H
VO
2
TSD
OSC
OSC
330F
VIN VIN
330F + -
SW INV VIN FB 3
FB RT
+ CURRENT LIMIT GND
7 3 VIN SW FB INV EN GND RT
FB RT
CURRENT LIMIT GND
4
6
6
0.1F
390k
0.1F
390k
Fig.23 No. 1 2 3 4 5 6 7 8 Pin name VIN SW FB INV EN RT GND PVIN Function Power supply input Output Error Amp output Output voltage feedback Enable Frequency setting resistor connection Ground Power system power supply input No. 1 2 3 4 5 6 7 FIN Pin name VIN SW FB GND INV RT EN -
Fig.24 Function Power supply input Output Error Amp output Ground Output voltage feedback Frequency setting resistor connection Enable Ground
(BD9001F)
(BD9781HFP)
VIN
8
VIN
EN/ SYNC ON/OFF L:OFF H:ON
1
7
220F
1F 220F 1F Vref SYNC
SOFT START
Vref 23k
SOFT START
INV
ERROR AMP
23k
INV ERROR AMP
6 +
PWM COMPARATOR LATCH RESET DRIVER SW
4 10k 150k
+ +
Vref
10k 33 H
VO
+ +
Vref
+
PWM COMPARATOR LATCH RESET DRIVER SW
33H
VO
150k 4700pF
2
TSD
VIN
1 OSC
TSD
VIN
4700pF GND EN VIN RT
OSC
330F
330F + CURRENT LIMIT GND FB RT
+ CURRENT LIMIT
4
N.C. INV SW FB
FB
7
GND
5 3 VIN RT FB EN/SINC SW GND INV 0.1F 390k
3 6
RT
0.1F
390k
Fig.25 No. 1 2 3 4 5 6 7 8 Pin name SW N.C. FB INV EN RT GND VIN Function Output Non Connection Error Amp Output Output voltage feedback Enable Frequency setting resistor connection Ground Power supply input No. 1 2 3 4 5 6 7 FIN Pin name VIN SW RT GND FB INV EN/SYNC -
Fig.26 Function Power supply input Output Frequency setting resistor connection Ground Error Amp output Output voltage feedback Enable/Synchronizing pulse input Ground
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6/16
2010.02 - Rev. B
BD9778F, BD9778HFP, BD9001F, BD9781HFP
Description of operations
Technical Note
ERROR AMP The ERROR AMP block is an error amplifier used to input the reference voltage (1 V typ.) and the INV pin voltage. The output FB pin controls the switching duty and output voltage Vo. These INV and FB pins are externally mounted to facilitate phase compensation. Inserting a capacitor and resistor between these pins enables adjustment of phase margin. (Refer to recommended examples on page 11.)
SOF T START The SOFT START block provides a function to prevent the overshoot of the output voltage Vo through gradually increasing the normal rotation input of the error amplifier when power supply turns ON to gradually increase the switching Duty. The soft start time is set to 5 msec (Typ.).
ON/OFF(BD9778F/HF P,BD9781HFP) Setting the EN pin to 0.8 V or less makes it possible to shut down the circuit. Standby current is set to 0 A (Typ.). Furthermore, on the BD9781HFP, applying a pulse having a frequency higher than set oscillation frequency to the EN/SYNC pin allows for external synchronization (up to +50% of the set frequency).
PWM COM PARATOR The PWM COMPARATOR block is a comparator to make comparison between the FB pin and internal triangular wave and output a switching pulse. The switching pulse duty varies with the FB value and can be set in the range of 0 to 100%.
OSC(Oscillator) The OSC block is a circuit to generate a triangular wave that is to be input in the PWM comparator. Connecting a resistor to the RT pin enables setting of oscillation frequency.
TSD(Thermal Shut Down) In order to prevent thermal destruction/thermal runaway of this IC, the TSD block will turn OFF the output when the chip temperature reaches approximately 150C or more. When the chip temperature falls to a specified level, the output will be reset. However, since the TSD is designed to protect the IC, the chip junction temperature should be provided with the thermal shutdown detection temperature of less than approximately 150C.
CURREN T LIMIT While the output POWER P-ch MOS FET is ON, if the voltage between drain and source (ON resistance load current) exceeds the reference voltage internally set with the IC, this block will turn OFF the output to latch. The overcurrent protection detection values have been set as shown below: BD9781HFP . . . 8A(Typ.) BD9001F,BD9778F/HFP . . . 4A(Typ.) Furthermore, since this overcurrent protection is an automatically reset, after the output is turned OFF and latched, the latch will be reset with the RESET signal output by each oscillation frequency. However, this protection circuit is only effective in preventing destruction from sudden accident. It does not support for the continuous operation of the protection circuit (e.g. if a load, which significantly exceeds the output current capacitance, is normally connected). Furthermore, since the overcurrent protection detection value has negative temperature characteristics, consider thermal design.
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7/16
2010.02 - Rev. B
BD9778F, BD9778HFP, BD9001F, BD9781HFP
Timing chart (BD9781HFP) - While in basic operation mode VIN
Technical Note
Internal OSC
FB
SW
EN/SYNC Fig.27 While in overcurrent protection mode
IO
Internal OSC
FB
SW
Output short circuit
Auto reset
Auto reset
Auto reset
Auto reset
Fig.28 External synchronizing function (BD9781HFP) In order to activate the external synchronizing function, connect the frequency setting resistor to the RT pin and then input a synchronizing signal to the EN/SYNC pin. As the synchronizing signal, input a pulse wave higher than a frequency determined with the setting resistor (RT). On the BD9781HFP, design the frequency difference to be within 50%. Furthermore, set the pulse wave duty between 10% and 90%.
FSYNC
: For RT only Internal OSC : For external synchronization Fig.29
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8/16
2010.02 - Rev. B
BD9778F, BD9778HFP, BD9001F, BD9781HFP
Description of external components
Technical Note
VIN
L
VIN
C Cin
SW
+ Di CO
VO
R1
RT
INV
RT
CT
SS GND
CSS
FB
CC RC
R2
Fig.30
Design procedure Vo = Output voltage, Vin (Max.) = Maximum input voltage Io (Max.) = Maximum load current, f = Oscillation frequency 1. Setting or output voltage Output voltage can be obtained by the formula shown below. VO=1 x (1+R1/R2) Use the formula to select the R1 and R2. Furthermore, set the R2 to 30 k or less. Select the current passing through the R1 and R2 to be small enough for the output current. 2. Selection of coil (L) The value of the coil can be obtained by the formula shown below: L=(VIN-VO) x VO / (VIN x f x IO) IO: Output ripple current f = Operating frequency Io should typically be approximately 20 to 30% of Io. If this coil is not set to the optimum value, normal (continuous) oscillation may not be achieved. Furthermore, set the value of the coil with an adequate margin so that the peak current passing through the coil will not exceed the rated current of the coil. 5=1 x (1+R1/10k) Calculation example
When Vo = 5 V and R2 = 10 k ,
R1=40k
When VIN = 13.2 V, Vo = 5 V, Io = 2 A, and f = 100 kHz, L=(13.2-5) x 5/13.2 x 1/100k x 1/(2 x 0.3) =51.8H 47
L=47H
3. Selection of output capacitor (Co) The output capacitor can be determined according to the output ripple voltage Vo (p-p) required. Obtain the required ESR value by the formula shown below and then select the capacitance. IL=(VIN-VO) x VO/(L x f x VIN) Vpp=IL x ESR+(IL x Vo)/(2 x Co x f x VIN) Set the rating of the capacitor with an adequate margin to the output voltage. Also, set the maximum allowable ripple current with an adequate margin to IL. Furthermore, the output rise time should be shorter than the soft start time. Select the output capacitor having a value smaller than that obtained by the formula shown below. 3.5m x (ILimit-Io(Max)) CMax= Vo
VIN=13.2V, Vo=5V, L=100H, f=100kHz IL=(13.2-5) x 5/(100 x 10-6 x 100 x 103 x 13.2) 0.31
IL=0.31A
When ILimit: 2 A, Io (Max) = 1 A, and Vo = 5V,
CMax=3.5m x (2-1)/5 =700
ILimit:2A(BD9778F/HFP,BD9001F), 4A(BD9781HFP) If this capacitance is not optimum, faulty startup may result. ( 3.5m is soft start time(min.))
CMax=700F
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9/16
2010.02 - Rev. B
BD9778F, BD9778HFP, BD9001F, BD9781HFP
Design procedure 4. Selection of diode Set diode rating with an adequate margin to the maximum load current. Also, make setting of the rated inverse voltage with an adequate margin to the maximum input voltage. A diode with a low forward voltage and short reverse recovery time will provide high efficiency. Calculation example
Technical Note
When VIN = 36 V and Io = (max.) 2 A, Select a diode of rated current of 2 A or more and rated withstand voltage of 36 V or more.
5. Selection of input capacitor Two capacitors, ceramic capacitor CIN and bypass capacitor C, should be inserted between the VIN and GND.Be sure to insert a ceramic capacitor of 1 to 10 F for the C. The capacitor C should have a low ESR and a significantly large ripple current. The ripple current IRMS can be obtained by the following formula: IRMS=IO X VO X (Vin-VO)/ Vin2 Select capacitors that can accept this ripple current. If the capacitance of CIN and C is not optimum, the IC may malfunction. 6. Setting of oscillation frequency Referring Fig. 34 and Fig. 35 on the following page, select R for the oscillation frequency to be used. Furthermore, in order to eliminate noises, be sure to connect ceramic capacitors of 0.1 to 1.0 F in parallel. 7. Setting of phase compensation (Rc and Cc) The phase margin can be set through inserting a capacitor or a capacitor and resistor between the INV pin and the FB pin. Each set value varies with the output coil, capacitance, I/O voltage, and load. Therefore, set the phase compensation to the optimum value according to these conditions. (For details, refer to Application circuit on page 11.) If this setting is not optimum, output oscillation may result.
When VIN = 13.2 V, Vo = 5 V, and Io = 1 A, IRMS=1 X 5 X (13.2-5)/(13.2)2 =0.485
IRMS=0.485A
* The set values listed above are all reference values. On the actual mounting of the IC, the characteristics may vary with the routing of wirings and the types of parts in use. In this connection, it is recommended to thoroughly verify these values on the actual system prior to use.
Directions for pattern layout of PCB
1
GND
BD9778HFP
GND
INV
SW
VIN
RT R3 Cx1 C3
EN
RT
FB
CT
3
SIGNAL GND
2
C Cin
8
L
8
L O A D
4
Cx2
R2
Co GND
R1
5
6
Fig.31
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10/16
2010.02 - Rev. B
BD9778F, BD9778HFP, BD9001F, BD9781HFP
Technical Note
Di
Cin
C
L
RT CT Cx1 R3 Di RT CT Cx1 R3 C3 Cx2 R2 500 R1 600 700
C3
Co
Cx2 R2
Cin L Co
200
C
R1
Fig.32 BD9001F reference layout pattern
As shown above, design the GND pattern as large area as possible within inner layer. Gray zones indicate GND.
500
Fig.33 BD9781HFP reference layout pattern
OSCILATING FREQUENCY : fosc[kHz]
450 400 350 300 250 200 150 100 50 0 100 200 300 400 500 600 700 800
OSCILATING FREQUENCY : fosc[kHz]
300
250
200
150
100
50 50 100
300
400
800
OSCILATING FREQUENCY SETTING RESISTANCE : RT[k]
OSCILATING FREQUENCY SETTING RESISTANCE : RT [k]
Fig.34 RT vs fOSC (BD9781HFP/BD9778F/HFP)
Fig.35 RT vs fOSC BD9001F
Phase compensation setting procedure 1. Application stability conditions The following section describes the stability conditions of the negative feedback system. Since the DC/DC converter application is sampled according to the switching frequency, GBW (frequency at 0-dB gain) of the overall system should be set to 1/10 or less of the switching frequency. The following section summarizes the targeted characteristics of this application. At a 1 (0-dB) gain, the phase delay is 150 or less (i.e., the phase margin is 30 or more). The GBW for this occasion is 1/10 or less of the switching frequency. Responsiveness is determined with restrictions on the GBW. To improve responsiveness, higher switching frequency should be provided. Replace a secondary phase delay (-180) with a secondary phase lead by inserting two phase leads, to ensure the stability through the phase compensation. Furthermore, the GBW (i.e., frequency at 0-dB gain) is determined according to phase compensation capacitance provided for the error amplifier. Consequently, in order to reduce the GBW, increase the capacitance value. (1) Typical integrator (Low pass filter) (2) Open loop characteristics of integrator
(a) A Gain [dB] 0 Phase -90 [] 0 -90 Phase margin -180
f
-20dB/decade GBW(b)
f
FB A
+
Feedback
R -
C
-180
Since the error amplifier is provided with (1) or (2) phase compensation, the low pass filter is applied. In the case of the DC/DC converter application, the R becomes a parallel resistance of the feedback resistance.
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11/16
2010.02 - Rev. B
BD9778F, BD9778HFP, BD9001F, BD9781HFP
2. For output capacitors having high ESR, such as electrolyte capacitor
Technical Note
For output capacitors that have high ESR (i.e., several ), the phase compensation setting procedure becomes comparatively simple. Since the DC/DC converter application has a LC resonant circuit attached to the output, a -180 phase-delay occurs in that area. If ESR component is present, howeve r, a +90 phase-lead occurs to shift the phase delay to -90. Since the phase delay should be set within 150, it is a very effective method but tends to increase the ripple component of the output voltage. (1) LC resonant circuit
VCC
(2) With ESR provided
VCC
L + C
VO
L
VO
)
RESR C
fr =
1
[Hz]
At this resonance point, a -180 phase-delay occurs. A -90 phase-delay occurs. According to changes in phase characteristics, due to the ESR, only one phase lead should be inserted. For this phase lead, select either of the methods shows below: (3) Insert feedback resistance in the C.
VO C1 R1 INV R2 A + R2 FB INV C2 R1 A + FB
(4) Insert the R3 in integrator.
VO R3 C2
To cancel the LC resonance, the frequency to insert the phase lead should be set close to the LC resonant frequency. The settings above have are estimated. Consequently, the settings may be adjusted on the actual system. Furthermore, since these characteristics vary with the layout of PCB loading conditions, precise calculations should be made on the actual system. 3. For output capacitors having low ESR, such as low impedance electrolyte capacitor or OS-CON In order to use capacitors with low ESR (i.e., several tens of m), two phase-leads should be inserted so that a -180 phase-delay, due to LC resonance, will be compensated. The following section shows a typical phase compensation procedure. (1) Phase compensation with secondary phase lead
VO R1 C1 INV R2 A + FB R3
C2
To set phase lead frequency, insert both of the phase leads close to the LC resonant frequency. According to empirical rule, setting the phase lead frequency f Z2 with R3 and C2 lower than the LC resonant frequency fr, and the phase lead frequency fZ1 with the R1 and C1 higher than the LC resonant frequency fr, will provide stable application conditions.
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12/16
(
2010.02 - Rev. B
BD9778F, BD9778HFP, BD9001F, BD9781HFP
Measurement of open loop of DC/DC converter
Technical Note
To measure the open loop of DC/DC converter, use the gain phase analyzer or FRA to measure the frequency r A characteristics. 1. Check to ensure output causes no oscillation at the maximum load in closed loop. 2. Isolate (1) and (2) and insert Vm (with amplitude of approximately 100 mVpp). 3. Measure (probe) the oscillation of (1) to that of (2). Furthermore, the phase margin can also be measured with the load responsiveness. Measure variations in the output voltage when instantaneously changing the load from no load to the maximum load. Even though ringing phenomenon is caused, due to low phase margin, no ringing takes place. Phase margin is provided. However, no specific phase margin can be probed.
DC/DC converter controller
VO +
~
Vm
RL
Maximum load Load 0 Output voltage Inadequate phase margin
Adequate phase margin t
Heat loss
C C
The heat loss W of the IC can be obtained by the formula shown below: Vo W=Ron X Io2 X + VIN X ICC + Tr X VIN X Io X f VIN Ron: ON resistance of IC (refer to pages 4 and 5.) Io: Load current Vo: Output voltage VIN: Input voltage Icc: Circuit current (Refer to pages 2 and 3) Tr: Switching rise/fall time (Approximately 40 nsec) f : Oscillation frequency Tr VIN SW waveform GND 2 T= 1 f
1 1 Ron X Io2 2 2X 1 1 X Tr X X VIN X Io T 2 =Tr X VIN X Io X f
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13/16
2010.02 - Rev. B
BD9778F, BD9778HFP, BD9001F, BD9781HFP
SW
VIN VIN VIN
Technical Note
FB BD9778F/HFP, BD9781HFP
VREF VIN
RT
VREF
INV
VREF
50k SW 10k RT 2k 300k VIN FB 1k INV 1k
EN BD9778F/HFP, BD9001F
VIN
FB BD9001F
VREF VIN
EN/SYNC BD9781HFP
VREGA
VIN EN 300k FB 1k 1k EN/SYNC 222 k 145 k 221 k 2k
250k
139 k
Fig.36 Equivalent circuit Notes for use 1) Absolute maximum ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses. Furthermore, don't turn on the IC with a fast rising edge of VIN. ( rise time << 10V / sec ) 2) GND potential GND potential should maintain at the minimum ground voltage level. Furthermore, no terminals should be lower than the GND potential voltage including an electric transients. 3) Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 4) Inter-pin shorts and mounting errors Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any connection error or if positive and ground power supply terminals are reversed. The IC may also be damaged if pins are shorted together or are shorted to other circuits power lines. 5) Operation in strong electromagnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction. 6) Inspection with set printed circuit board When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to, or removing it from a jig or fixture, during the inspection process. Ground the IC during assembly steps as an antistatic measure. Use similar precaution when transporting and storing the IC.
Resistor
(Pin A) (Pin B) C
Transistor (NPN)
B E
(Pin A) Parasitic element
GND N P+ N N P layer N Parasitic element GND Parasitic element N P layer GND GND P P+ P+ N N B E P P+ (PIN B) C GND
Fig.37 Typical simple construction of monolithic IC
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Parasitic element
14/16
2010.02 - Rev. B
BD9778F, BD9778HFP, BD9001F, BD9781HFP
Technical Note
7) IC pin input (Fig. 37) This monolithic IC contains P+ isolation and P substrate layers between adjacent elements to keep them isolated. P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode or transistor. For example, the relation between each potential is as follows: When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode. When Pin B > GND > Pin A, the P-N junction operates as a parasitic transistor. Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage toan input pin, should not be used. 8) Ground wiring pattern It is recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB, so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Prevent fluctuations in the GND wiring pattern of external parts. 9) Temperature protection (thermal shut down) circuit This IC has a built-in temperature protection circuit to prevent the thermal destruction of the IC. As described above, be sure to use this IC within the power dissipation range. Should a condition exceeding the power dissipation range continue, the chip temperature Tj will rise to activate the temperature protection circuit, thus turning OFF the output power element. Then, when the tip temperature Tj falls, the circuit will be automatically reset. Furthermore, if the temperature protection circuit is activated under the condition exceeding the absolute maximum ratings, do not attempt to use the temperature protection circuit for set design. 10) On the application shown below, if there is a mode in which VIN and each pin potential are inverted, for example, if the VIN is short-circuited to the Ground with external diode charged, internal circuits may be damaged. To avoid damage, it is recommended to insert a backflow prevention diode in the series with VIN or a bypass diode between each pin and VIN.
Bypass diode Backflow prevention diode
Vcc
Pin
Fig.35
Thermal derating characteristics HRP7
10 9 PD[W] 8 7 6 5 4 3 2 1 0 1.4W 25 50 75 100 125 150 0.1 0 0 25 50 2.3W 0.2 BD9001F BD9778F 5.5W 0.5 0.4 0.3 7.3W PD[W] 0.8 0.7 0.6
SOP8
75
100
125
150
Single piece of IC 3 PCB size: 70 x 70 x 1.6 mm (PCB incorporates thermal via.) Copper foil area on the front side of PCB: 10.5 x 10.5 mm2 2-layer PCB (Copper foil area on the reverse side of PCB: 15 x 15 mm2) 2-layer PCB (Copper foil area on the reverse side of PCB: 70 x 70 mm2) 4-layer PCB (Copper foil area on the reverse side of PCB: 70 x 70 mm2)
Single piece of IC When mounted on ROHM standard PCB (Glass epoxy PCB of 70 mm x 70 mm x 1.6 mm)
Fig.39 www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
Fig.40
15/16
2010.02 - Rev. B
BD9778F, BD9778HFP, BD9001F, BD9781HFP
Selection of order type
Technical Note
B
D
9
7
7
8
H
F
P
-
T
R
Part No.
Part No. 9778 = 36V/2A 9781 = 36V/4A 9001 = 50V/2A
Package F = SOP8 HFP = HRP7
Taping type E2 = Reel-type embossed carrier tape (SOP8) TR = Reel-type embossed carrier tape (HRP7)
SOP8

5.00.2 (MAX 5.35 include BURR)
8 7 6 5
Tape
+6 4 -4 0.90.15 0.3MIN
Embossed carrier tape 2500pcs E2
The direction is the 1pin of product is at the upper left when you hold
Quantity Direction of feed
6.20.3
4.40.2
( reel on the left hand and you pull out the tape on the right hand
)
12
3
4
0.595 1.50.1 +0.1 0.17 -0.05 S 0.1 0.11 S
1.27 0.420.1
1pin
Direction of feed
(Unit : mm)
Reel
Order quantity needs to be multiple of the minimum quantity.
HRP7
9.3950.125 (MAX 9.745 include BURR) 1.0170.2 8.820.1 (5.59) 1.9050.1

Tape Quantity Direction of feed Embossed carrier tape 2000pcs TR
The direction is the 1pin of product is at the upper right when you hold
1.5230.15
0.8350.2
10.540.13
8.00.13
(7.49)
( reel on the left hand and you pull out the tape on the right hand
1pin
)
0.8875
12 34 5 6 7
+5.5 4.5 -4.5 0.730.1 +0.1 0.27 -0.05 S
0.080.05
1.27
0.08 S
Direction of feed
(Unit : mm)
Reel
Order quantity needs to be multiple of the minimum quantity.
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16/16
2010.02 - Rev. B
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us.
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http://www.rohm.com/contact/
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R1010A


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